Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure

US8471340B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Alan B. Botula · South Burlington, US
• John J. Ellis-Monaghan · Grand Isle, US
• Alvin J. Joseph · Williston, US
• Max G. Levy · South Burlington, US
• Richard A. Phelps · Colchester, US
• James A. Slinkman · Montpelier, US
• Randy L. Wolf · South Burlington, US

Key dates

• Filing date: Nov 30, 2009
• Grant date: Jun 25, 2013
• Expiry date: Jun 26, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.