Three-dimensional stacked structure semiconductor device having through-silicon via and signaling method for the semiconductor device
US8471362B2 · kind B2 · utility
20Cited by
2References
18Claims
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Key dates
| Filing date | Apr 5, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Nov 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.