Duty cycle correction in a delay-locked loop
US8471617B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jan 3, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.