Offset tiles in vector graphics
US8471862B2 · kind B2 · utility
2Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jul 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient rendering method for processing computer graphics in tiles. First a frame of data, typically at least one polygon, is received for rendering. While rendering a polygon the tile for the polygon is assigned so that it minimizes the number of the tiles needed for processing the polygon. It is possible to compute an offset value between the static tiles and the assigned tiles. If the offset value is computed, the rendering into an actual screen may be based on that.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.