Input output bridging
US8473658B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Oct 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.