Optimizing power usage by processor cores based on architectural events
US8473766B2 · kind B2 · utility
4Cited by
16References
1Claims
0Family size
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Key dates
| Filing date | Sep 10, 2012 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Sep 10, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.