Parity error checking and compare using shared logic circuitry in a ternary content addressable memory
US8473832B2 · kind B2 · utility
2Cited by
20References
22Claims
0Family size
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Key dates
| Filing date | Aug 19, 2009 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Oct 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.