Striping methodology for maskless lithography
US8473877B2 · kind B2 · utility
26Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Sep 6, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/3174
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure involves a method of performing a maskless lithography process. The method includes receiving a computer layout file for an integrated circuit (IC) device. The layout file contains a plurality of IC sections. The method includes separating the computer layout file into a plurality of sub-files. The method includes striping the plurality of sub-files concurrently using a plurality of computer processors, thereby generating a plurality of striped sub-files. The method includes transferring the plurality of striped sub-files to a maskless lithography system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.