Lithographically enhanced edge determination
US8473878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Nov 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
During a calculation technique, at least a portion of a target pattern associated with an integrated-circuit design is modified so that polygons in the target pattern, which represent features in the design, result in acceptable accuracy during a photolithographic process that fabricates the target pattern on a semiconductor die. In particular, a set of polygon parameters associated with the polygons are modified, as needed, so that a cost function that corresponds to a difference between a modified target pattern and an estimated target pattern produced during the photolithographic process meets a termination criterion. A mask pattern that can fabricate the modified target pattern on the semiconductor die is calculated using an inverse optical calculation in which the modified target pattern is at an image plane of an optical path associated with the photolithographic process and the mask pattern is at an object plane of the optical path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.