Synchronization of parallel memory accesses in a dataflow circuit
US8473880B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2010 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Jul 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Approaches for creating a pipelined circuit design from a high level language (HLL) specification. In one embodiment, the HLL specification is translated into an intermediate level language specification of operations of the pipelined circuit design, and a data dependency graph of the operations is created. A sequence of operations that is bounded by two write operations and that has no intervening write operations between the two write operations is identified, along with two or more read operations within the sequence. A pipelined design specification is generated from the dependency graph and hardware components associated with the operations in the intermediate level language specification. At least two of the components corresponding to the two or more read operations access a memory in parallel, and each component corresponding to the two or more read and the two write operations requires a synchronization token as input and outputs a synchronization token upon completion of the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.