Generation of cache architecture from a high-level language description
US8473904B1 · kind B1 · utility
3Cited by
9References
19Claims
0Family size
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Key dates
| Filing date | Jan 16, 2008 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Apr 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.