Iterative rinse for semiconductor fabrication
US8476003B2 · kind B2 · utility
1Cited by
1References
19Claims
0Family size
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Key dates
| Filing date | Mar 9, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Oct 5, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0206
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An iterative rinse for fabrication of semiconductor devices is described. The iterative rinse includes a plurality of rinse cycles, wherein each of the plurality of rinse cycles has a different resistivity. The plurality of rinse cycles may include a first rinse of a semiconductor substrate with de-ionized (DI) water and carbon dioxide (CO2), followed by a second rinse the semiconductor substrate with DI water and CO2. The first rinse has a first resistivity; the second rinse has a second resistivity lower than the first resistivity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.