Saving energy mode (SEM) for an interleaved power factor correction (PFC) converter
US8476879B2 · kind B2 · utility
10Cited by
10References
17Claims
0Family size
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Key dates
| Filing date | Jan 27, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of controlling a power factor correction (PFC) converter having a first PFC sub-circuit and a second PFC sub-circuit determines when to transition the PFC converter between an interleaved mode and a saving energy mode (SEM). The method includes generating an amplified error signal based on a monitored output voltage of the PFC converter. The second PFC sub-circuit is disabled in response to the amplified error signal being less than a first threshold value and enabled in response to the amplified error signal exceeding a second threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.