Method and apparatus for amplifying a time difference
US8476972B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 11, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Sep 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG04F10/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A time amplifier circuit has first and second inverters and first and second pull-down paths. Each inverter includes a first NMOS transistor and a first PMOS transistor. A source of the first NMOS transistor is coupled to a ground node directly or through a first additional NMOS transistor having a gate coupled to a respective input node. The first and second inverters are coupled to first and second input nodes and to first and second output nodes, respectively. The first pull-down path is from the first output node to the ground node and is enabled in response to the first input signal and the second output signal being high. The second pull-down path is from the second output node to ground and is enabled in response to the second input signal and the first output signal being high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.