Ferroelectric memory write-back
US8477522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Feb 6, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/2275
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.