Semiconductor memory device
US8477554B2 · kind B2 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Sep 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a plurality of layers each including a memory cell array and which are stacked over each other; and at least one power plane for supplying power to the layers. The power plane includes a region to which a power voltage is applied and a region to which a ground voltage is applied. The region to which a power voltage is applied is located adjacent to the region to which a ground voltage is applied, and forms a decoupling capacitor therebetween to decouple an influx of power noise to the layers or generation of power noise in the layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.