Method and apparatus for reducing processor cache pollution caused by aggressive prefetching
US8478942B2 · kind B2 · utility
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5References
19Claims
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Key dates
| Filing date | Sep 27, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jan 10, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.