Performing a multiply-multiply-accumulate instruction
US8478969B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a processor having multiple execution units, at least one of which includes a circuit having a multiply-accumulate (MAC) unit including multiple multipliers and adders, and to execute a user-level multiply-multiply-accumulate instruction to populate a destination storage with a plurality of elements each corresponding to an absolute value for a pixel of a pixel block. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.