Patent · US Active

Integrated circuit arrangement for test inputs

US8479070B2 · kind B2 · utility

0Cited by

11References

16Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Ulrich Baur · Holzgerlingen, DE
Lawrence D. Curley · Endwell, US
Ronald J. Frishmuth · Poughkeepsie, US
Ralf Ludewig · Schenefeld, DE
Ching-Lung Tong · Highland Mills, US
Tobias Webel · Eppelheim, DE

Key dates

Filing date	Jun 24, 2010
Grant date	Jul 2, 2013
Priority date	—
Expiry date	Aug 24, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/3172
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.