Technique for honoring multi-cycle path semantics in RTL simulation
US8479128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2011 |
| Grant date | Jul 2, 2013 |
| Priority date | — |
| Expiry date | Sep 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced RTL simulation including information regarding multi-cycle paths is provided. The multi-cycle path information, which is available in the design constraint file, can be used for timing analysis during RTL simulation. This information can advantageously augment the RTL simulation engine to approximate the cycle delays at the destination registers, thereby providing a more realistic approximation of circuit behavior at the RTL level. Notably, RTL simulation is orders of magnitude faster than gate level simulation. Moreover, design bugs associated with multi-cycle paths are more easily corrected during RTL simulation compared to waiting until the gate level simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.