Method for manufacturing a semiconductor device with impurity doped oxide semiconductor
US8481377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2011 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Mar 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
It is an object to provide a semiconductor device including an oxide semiconductor, in which miniaturization of a transistor is achieved and the concentration of an electric field is relieved. The width of a gate electrode is reduced and a space between a source electrode layer and a drain electrode layer is shortened. By adding a rare gas in a self-alignment manner with the use of a gate electrode as a mask, a low-resistance region in contact with a channel formation region can be provided in an oxide semiconductor layer. Accordingly, even when the width of the gate electrode, that is, the line width of a gate wiring is small, the low-resistance region can be provided with high positional accuracy, so that miniaturization of a transistor can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.