Semiconductor device
US8482097B2 · kind B2 · utility
0Cited by
2References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 7, 2012 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 7, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/40
Abstract
A method of manufacturing a semiconductor device including a plurality of capacitors each of which has bottom electrode, dielectric layer, and top electrode includes stacking a bottom electrode layer, a dielectric layer and an top electrode layer, patterning the top electrode layer to form a plurality of top electrodes arranged in a column, forming a mask pattern that covers the plurality of top electrodes and leaves an end part of the outermost top electrode of the arrangement of the plurality of top electrodes exposed, and patterning the dielectric layer using the mask pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.