Semiconductor package
US8482133B2 · kind B2 · utility
2Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2011 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package is provided. The semiconductor package includes a package substrate, a plurality of semiconductor chips, and a plurality of connection terminals. The package substrate includes a center portion, which has a first recess with a portion of a top of the package substrate removed, and an edge portion that has a plurality of second recesses. Each second recess has a portion of a bottom of the package substrate removed. The plurality of semiconductor chips are mounted in the first recess, and the plurality of connection terminals are respectively disposed in the second recesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.