Data path for multi-level cell memory, methods for storing and methods for utilizing a memory array
US8482979B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 2012 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Mar 27, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories, data paths, methods for storing, and methods for utilizing are disclosed, including a data path for a memory using multi-level memory cells to provide storage of multiple bits per memory cell. One such data path includes a bit mapping circuit and a data converter circuit. Such a bit mapping circuit can be configured to map bits of the original data to an intermediate arrangement of bits and such a data converter circuit can be configured to receive the intermediate arrangement of bits and convert the intermediate arrangement of bits into intermediate data corresponding to a memory state to be stored by memory cells of a memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.