Memory edge cell
US8482990B2 · kind B2 · utility
2Cited by
0References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2011 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 28, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/417
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.