Programmable addressing circuitry for increasing memory yield
US8483006B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2011 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.