Digital architecture for DFT/IDFT hardware
US8484278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2007 |
| Grant date | Jul 9, 2013 |
| Priority date | — |
| Expiry date | Aug 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.