Method for forming an integrated circuit level by sequential tridimensional integration
US8486817B2 · kind B2 · utility
2Cited by
4References
8Claims
0Family size
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Key dates
| Filing date | Jun 4, 2010 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jan 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a level of a tridimensional structure on a first support in which components are formed, including the steps of forming, on a second semiconductor support, a single-crystal semiconductor substrate with an interposed thermal oxide layer; placing the free surface of the single-crystal semiconductor substrate on the upper surface of the first support; eliminating the second semiconductor support; and thinning down the thermal oxide layer down to a thickness capable of forming a gate insulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.