Method of manufacturing an integrated semiconductor substrate structure with device areas for definition of GaN-based devices and CMOS devices
US8487316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2010 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Oct 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/08
Abstract
An integrated semiconductor substrate structure is disclosed. In one aspect, the structure includes a substrate, a GaN-heterostructure and a semiconductor substrate layer. The GaN heterostructure is present in a first device area for definition of GaN-based devices, and is covered at least partially with a protection layer. The semiconductor substrate layer is present in a second device area for definition of CMOS devices. At least one of the GaN heterostructure and the semiconductor substrate layer is provided in at least one trench in the substrate, so that the GaN heterostructure and the semiconductor substrate layer are laterally juxtaposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.