Planar MOSFET with textured channel and gate
US8487367B2 · kind B2 · utility
0Cited by
4References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 24, 2010 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Nov 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A semiconductor device is disclosed that includes a semiconductor substrate having a channel region and respective source and drain regions formed on opposite sides of the channel region. The channel region includes at least one pore. A gate is formed on the semiconductor substrate between the source and drain regions and includes at least one pin received by respective ones of the at least one pore. A dielectric layer is disposed between the gate and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.