Phase locked loop with adaptive biasing
US8487677B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop including first and second charge pumps, a voltage buffer and a bias generator for adaptive biasing for improved performance. A voltage controlled oscillator, feedback circuit and phase detector portions may be provided to operate similar to conventional configurations. The first charge pump receives an adjust signal, such as from the phase detector, and selectively charges an intermediate node. The second charge pump receives the adjust signal and selectively charges a control node developing the control voltage for the VCO. A loop filter capacitor is referenced to the intermediate node. The voltage buffer, replacing the loop filter resistor, buffers the intermediate node and drives the control node. The bias generator converts the control voltage to a converter bias current based on the control voltage and adjusts the charge pump currents and a bias current of the voltage buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.