Semiconductor memory device and test method thereof
US8488393B2 · kind B2 · utility
1Cited by
3References
23Claims
0Family size
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Key dates
| Filing date | Jul 26, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Jan 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of first pads and a plurality of memory unit blocks. The plurality of first pads are configured to input/output data in a test mode. The plurality of memory unit blocks each include a plurality of second pads configured to input/output data in a normal mode, and a plurality of data path selection units configured to connect internal circuits of the corresponding memory unit block to the plurality of first pads or the plurality of second pads in response to a unit block selection flag signal, a write enable signal, a read enable signal, and a mode control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.