Performing escape actions in transactions
US8489864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2009 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performing non-transactional escape actions within a hardware based transactional memory system. A method includes at a hardware thread on a processor beginning a hardware based transaction for the thread. Without committing or aborting the transaction, the method further includes suspending the hardware based transaction and performing one or more operations for the thread, non-transactionally and not affected by: transaction monitoring and buffering for the transaction, an abort for the transaction, or a commit for the transaction. After performing one or more operations for the thread, non-transactionally, the method further includes resuming the transaction and performing additional operations transactionally. After performing the additional operations, the method further includes either committing or aborting the transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.