Command protocol for adjustment of write timing delay

US8489912B2 · kind B2 · utility

Assignee

• ATI Technologies ULC · CA

Inventors

• Aaron Nygren · Birkenfeld, DE
• Ming-Ju Edward Lee · San Jose, US
• Shadi M. Barakat · Sunnyvale, US
• Xiaoling Xu · Santa Clara, US
• Toan Duc Pham · Cedar Park, US
• Warren Fritz Kruger · Sunnyvale, US
• Michael John Litt · Toronto, CA

Key dates

• Filing date: Jul 30, 2010
• Grant date: Jul 16, 2013
• Expiry date: Oct 5, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1689
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.