Processing resource allocation within an integrated circuit supporting transaction requests of different priority levels
US8490107B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2011 |
| Grant date | Jul 16, 2013 |
| Priority date | — |
| Expiry date | Aug 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/805
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An integrated circuit 2 includes a plurality of transaction sources 6, 8, 10, 12, 14, 16, 18, 20 communicating via a ring-based interconnect 30 with shared caches 22, 24 each having an associated POC/POS 30, 34 and serving as a request servicing circuit. The request servicing circuits have a set of processing resources 36 that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.