Production of a transistor gate on a multibranch channel structure and means for isolating this gate from the source and drain regions

US8492232B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Thomas Ernst · Morette, FR
• Christian Isheden · Dresden, DE

Key dates

• Filing date: Jul 25, 2011
• Grant date: Jul 23, 2013
• Expiry date: Sep 19, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6735

Abstract

A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers.