Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer
US8492868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jul 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.