Semiconductor package having a cavity structure
US8492883B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2008 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.