Clock delay circuit and delay locked loop including the same
US8493116B2 · kind B2 · utility
1Cited by
23References
20Claims
0Family size
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Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.