Storage circuitry and method with increased resilience to single event upsets
US8493120B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Mar 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.