Memory having asynchronous read with fast read output
US8493811B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 10, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit is disclosed. The memory circuit includes memory cells and asynchronous read decode logic configured to decode a received address and to select particular ones of the memory cells for reading. The read decode logic may be comprised of static, combinational logic, and thus the decoding of the received address may be conducted without the use of a clock signal or a cycle of a clock signal. Accordingly, a read operation may be conducted responsive to receiving the read address, without waiting for a subsequent clock edge. Furthermore, read output logic may also be asynchronous, and thus may provide data read from the memory cells without having to wait for a clock edge. The read output logic may include push-pull driver circuits coupled to global bit lines. The push-pull driver circuits may drive their corresponding global bit lines based on the data read from corresponding memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.