DSP engine with implicit mixed sign operands
US8495125B2 · kind B2 · utility
5Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | May 5, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor may have at least one multiplier unit which can be controlled to operate in a signed, an unsigned, or a mixed sign mode; a multiplier unit mode decoder coupled with the multiplier unit which receives location information of a first and second operands, wherein the multiplier mode decoder controls the multiplier unit when in the mixed sign mode depending on the location information to operate in a signed mode, an unsigned mode, or a combined signed/unsigned mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.