Implementing storage adapter performance optimization with hardware chains to select performance path
US8495259B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Aug 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0866
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to implement a particular performance path minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a data store configured to store a plurality of control blocks selectively arranged in one of a plurality of predefined chains. Each predefined chain defines a sequence of operations. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A resource handle structure is configured to select a predefined chain based upon a particular characteristic of the system. Each predefined chain is configured to implement a particular performance path to maximize performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.