Managing shared computer memory using multiple interrupts
US8495267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods to manage memory are provided. A particular method may include initiating a memory compression operation. The method may further include initiating a first interrupt configured to affect a first process executing on a processor in response to a first detected memory level. A second initiated interrupt may be configured to affect the first process executing on the processor in response to a second detected memory level, and a third interrupt may be initiated to affect the first process executing on the processor in response to a third detected memory level. At least of the first, the second, and the third detected memory levels are affected by the memory compression operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.