Write buffer for improved DRAM write access patterns

US8495286B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Cagri Balkesen · Zürich, CH
• Markus Buehler · Holzgerlingen, DE
• Rainer Dorsch · Reutlingen, DE
• Guenther Hutzl · Sindelfingen, DE
• Michael Kaufmann · Adliswil, CH
• Daniel Pfefferkorn · Rostock, DE
• David Rohr · Mannheim, DE
• Stefanie Scherzinger · Eppelheim, DE
• Thomas Schwarz · Helotes, US

Key dates

• Filing date: Dec 8, 2010
• Grant date: Jul 23, 2013
• Expiry date: Jul 14, 2031

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present invention relates to a method and respective system for operating a DRAM main memory. One buffer line is provided for multiple pages. When writing data to the buffer it is decided which to which buffer-line the data is written to based on its destination main memory address. A tuple consisting of lower memory address and data is stored. Data entered into the buffer-line will be sorted by page in case the line is flushed to the main memory. Sorting the buffer entries results in less page openings and closings, since the data is re-arranged by memory address and therefore in logical order. By using one line for multiple pages only a fraction of memory of a common set-associative cache is needed, thus decreasing the amount of overhead significantly.