Apparatus and method for detection and correction of denormal speculative floating point operand
US8495343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2010 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30025
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.