Patent · US Active

System and method for memory testing in electronic circuits

US8495436B1 · kind B1 · utility

3Cited by

6References

18Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Deepak Agrawal · Hyderabad, IN
Rachna Lalwani · Secunderabad, IN

Key dates

Filing date	Jun 17, 2012
Grant date	Jul 23, 2013
Priority date	—
Expiry date	Jun 17, 2032

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/4402
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.