Multi-level domino, bundled data, and mixed templates
US8495543B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 17, 2009 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Mar 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages. The data path and controller interact through a small number of key control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.