Multi-patterning lithography aware cell placement in integrated circuit design
US8495548B2 · kind B2 · utility
18Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Sep 29, 2011 |
| Grant date | Jul 23, 2013 |
| Priority date | — |
| Expiry date | Sep 29, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.