Method for fabricating a strained structure
US8497528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2010 |
| Grant date | Jul 30, 2013 |
| Priority date | — |
| Expiry date | Feb 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure for a field effect transistor on a substrate that includes a gate stack, an isolation structure and a source/drain (S/D) recess cavity below the top surface of the substrate disposed between the gate stack and the isolation structure. The recess cavity having a lower portion and an upper portion. The lower portion having a first strained layer and a first dielectric film. The first strained layer disposed between the isolation structure and the first dielectric film. A thickness of the first dielectric film less than a thickness of the first strained layer. The upper portion having a second strained layer overlying the first strained layer and first dielectric film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.